/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 *(C) Copyright 2006 Marvell International Ltd.  
 * All Rights Reserved 
 */

/**
**  FILENAME:       xllp_gpio_proc.h
**
**  PURPOSE: Contains all processor-level GPIO definitions.  Hardware platform-
**              specific GPIO macros, typedefs, and prototypes are found
**              in xllp_gpio_plat.h
**           Declares no storage.
**                  
**  Validity Notes: Only valid for processor code named Monahans.
**
******************************************************************************/

#ifndef __XLLP_GPIO_PROC_H__
#define __XLLP_GPIO_PROC_H__

#include "xllp_defs.h"
#define CONFIG_CPU_MONAHANS_LV
// XLLP GPIO API typedefs 

// Note: The registers preceded by "do not use" are valid but are read-modify
//       -write.  The registers after offset 0x400 perform the same operations
//       in a bitwise write-only fashion.  That removes the need for software
//       serialization handling (lock() and unlock())

typedef struct 
{
    XLLP_VUINT32_T gplr0;             /* Level Detect Reg. Bank 0 */
    XLLP_VUINT32_T gplr1;             /* Level Detect Reg. Bank 1 */
    XLLP_VUINT32_T gplr2;             /* Level Detect Reg. Bank 2 */
/*do not use*/    XLLP_VUINT32_T gpdr0;            /* Data Direction Reg. Bank 0 */
/*do not use*/    XLLP_VUINT32_T gpdr1;            /* Data Direction Reg. Bank 1 */
/*do not use*/    XLLP_VUINT32_T gpdr2;            /* Data Direction Reg. Bank 2 */
    XLLP_VUINT32_T gpsr0;            /* Pin Output Set Reg. Bank 0 */
    XLLP_VUINT32_T gpsr1;            /* Pin Output Set Reg. Bank 1 */
    XLLP_VUINT32_T gpsr2;            /* Pin Output Set Reg. Bank 2 */
    XLLP_VUINT32_T gpcr0;            /* Pin Output Clr Reg. Bank 0 */
    XLLP_VUINT32_T gpcr1;            /* Pin Output Clr Reg. Bank 1 */
    XLLP_VUINT32_T gpcr2;            /* Pin Output Clr Reg. Bank 2 */
/*do not use*/    XLLP_VUINT32_T grer0;   /* Ris. Edge Detect Enable Reg. Bank 0 */
/*do not use*/    XLLP_VUINT32_T grer1;   /* Ris. Edge Detect Enable Reg. Bank 1 */
/*do not use*/    XLLP_VUINT32_T grer2;   /* Ris. Edge Detect Enable Reg. Bank 2 */
/*do not use*/    XLLP_VUINT32_T gfer0;   /* Fal. Edge Detect Enable Reg. Bank 0 */
/*do not use*/    XLLP_VUINT32_T gfer1;   /* Fal. Edge Detect Enable Reg. Bank 1 */
/*do not use*/    XLLP_VUINT32_T gfer2;   /* Fal. Edge Detect Enable Reg. Bank 2 */
    XLLP_VUINT32_T gedr0;       /* Edge Detect Status Reg. Bank 0 */
    XLLP_VUINT32_T gedr1;       /* Edge Detect Status Reg. Bank 1 */
    XLLP_VUINT32_T gedr2;       /* Edge Detect Status Reg. Bank 2 */

    XLLP_VUINT32_T  reserved01[43];    /* addr. offset 0x074-0x0fc */
    XLLP_VUINT32_T  gplr3;             /* Level Detect Reg. Bank 3 */
    XLLP_VUINT32_T  reserved02[2];      /* addr. offset 0x104-0x108 */
/*do not use*/    XLLP_VUINT32_T gpdr3;            /* Data Direction Reg. Bank 3 */
    XLLP_VUINT32_T  reserved03[2];      /* addr. offset 0x110-0x114 */
    XLLP_VUINT32_T gpsr3;            /* Pin Output Set Reg. Bank 3 */
    XLLP_VUINT32_T  reserved04[2];      /* addr. offset 0x11c-0x120 */
    XLLP_VUINT32_T gpcr3;            /* Pin Output Clr Reg. Bank 3 */
    XLLP_VUINT32_T  reserved05[2];      /* addr. offset 0x128-0x12c */
/*do not use*/    XLLP_VUINT32_T grer3;   /* Ris. Edge Detect Enable Reg. Bank 3 */
    XLLP_VUINT32_T  reserved06[2];      /* addr. offset 0x134-0x138 */
/*do not use*/    XLLP_VUINT32_T gfer3;   /* Fal. Edge Detect Enable Reg. Bank 3 */
    XLLP_VUINT32_T  reserved07[2];      /* addr. offset 0x140-0x144 */
    XLLP_VUINT32_T gedr3;       /* Edge Detect Status Reg. Bank 3 */
    XLLP_VUINT32_T  reserved08[173];      /* addr. offset  */

// Beginning of new write-only, bit-significant registers
    /* addr. offset 0x400 */
    XLLP_VUINT32_T gsdr0;
    XLLP_VUINT32_T gsdr1;
    XLLP_VUINT32_T gsdr2;
    XLLP_VUINT32_T gsdr3;
    XLLP_VUINT32_T  reserved09[4];        /* addr. offset  */
    XLLP_VUINT32_T gcdr0;
    XLLP_VUINT32_T gcdr1;
    XLLP_VUINT32_T gcdr2;
    XLLP_VUINT32_T gcdr3;
    XLLP_VUINT32_T  reserved10[4];        /* addr. offset  */
    XLLP_VUINT32_T gsrer0;
    XLLP_VUINT32_T gsrer1;
    XLLP_VUINT32_T gsrer2;
    XLLP_VUINT32_T gsrer3;
    XLLP_VUINT32_T  reserved11[4];        /* addr. offset  */
    XLLP_VUINT32_T gcrer0;
    XLLP_VUINT32_T gcrer1;
    XLLP_VUINT32_T gcrer2;
    XLLP_VUINT32_T gcrer3;
    XLLP_VUINT32_T  reserved12[4];        /* addr. offset  */
    XLLP_VUINT32_T gsfer0;
    XLLP_VUINT32_T gsfer1;
    XLLP_VUINT32_T gsfer2;
    XLLP_VUINT32_T gsfer3;
    XLLP_VUINT32_T  reserved13[4];        /* addr. offset  */
    XLLP_VUINT32_T gcfer0;
    XLLP_VUINT32_T gcfer1;
    XLLP_VUINT32_T gcfer2;
    XLLP_VUINT32_T gcfer3;
    XLLP_VUINT32_T  reserved14[4];        /* addr. offset  */

} XLLP_GPIO_T, *P_XLLP_GPIO_T;


typedef enum 
{
    XLLP_GPIO_DIRECTION_IN = 0,
    XLLP_GPIO_DIRECTION_OUT = 1
} XLLP_GPIO_DIRECTION_T;


///////////////////////////////////////////////
//
//  Processor-specific GPIO constants start here.
//

#if defined(CONFIG_CPU_MONAHANS_PL) || defined(CONFIG_CPU_MONAHANS_L) || defined(CONFIG_CPU_MONAHANS_LV)
#define XLLP_GPIO_EXPANDER_NUMBER               2 // decimal
#define XLLP_GPIO_EXPANDER_PIN_NUMBER           16 // decimal
#define XLLP_GPIO_EXP0_ADDR                     0x74 // decimal
#define XLLP_GPIO_EXP1_ADDR                     0x75 // decimal
                                                                                          
// Max ID and Reserved GPIO IDs
#define XLLP_GPIO_ID_END                        127 //decimal
                                                                                          
#define XLLP_EXP_GPIO_START                     (127 + 1) // decimal
#define XLLP_EXP_GPIO_END                       (127 + XLLP_GPIO_EXPANDER_PIN_NUMBER * XLLP_GPIO_EXPANDER_NUMBER)
                                                                                          
#define XLLP_EXP0_GPIO_START                    (XLLP_GPIO_ID_END + 1)
#define XLLP_EXP0_GPIO_HALF                     (XLLP_GPIO_ID_END + (XLLP_GPIO_EXPANDER_PIN_NUMBER / 2))
#define XLLP_EXP0_GPIO_END                      (127 + XLLP_GPIO_EXPANDER_PIN_NUMBER)
                                                                                          
#define XLLP_EXP1_GPIO_START                    (XLLP_EXP0_GPIO_END + 1)
#define XLLP_EXP1_GPIO_HALF                     (XLLP_EXP0_GPIO_END + (XLLP_GPIO_EXPANDER_PIN_NUMBER / 2))
#define XLLP_EXP1_GPIO_END                      (127 + XLLP_GPIO_EXPANDER_PIN_NUMBER * XLLP_GPIO_EXPANDER_NUMBER)
#endif

// Max ID and Reserved GPIO IDs
#define XLLP_GPIO_ID_MAX                       127 // decimal
#define XLLP_GPIO_ID_INVALID_56                 56 // decimal
#define XLLP_GPIO_ID_INVALID_59                 59 // decimal
#define XLLP_GPIO_ID_INVALID_60                 60 // decimal
#define XLLP_GPIO_ID_INVALID_61                 61 // decimal
#define XLLP_GPIO_ID_INVALID_62                 62 // decimal

//
//  End of Processor-level GPIO constants
//
///////////////////////////////////////////////

#ifdef __cplusplus
extern "C"
{
#endif


/* Processor-level XLLP GPIO Function Prototypes */
#if defined(CONFIG_CPU_MONAHANS_PL) || defined(CONFIG_CPU_MONAHANS_L) || defined(CONFIG_CPU_MONAHANS_LV)
XLLP_STATUS_T XllpGpioExpanderRead( XLLP_UINT8_T expAddr,
                        XLLP_UINT8_T reg,
                        XLLP_UINT8_T *pval);
                                                                                          
XLLP_STATUS_T XllpGpioExpanderWrite(XLLP_UINT8_T expAddr,
                        XLLP_UINT8_T reg,
                        XLLP_UINT8_T val);
#endif

XLLP_STATUS_T XllpGpioGetLevel (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_LEVEL_T* pLevel);

XLLP_STATUS_T XllpGpioSetOutputLevel (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_LEVEL_T level);

XLLP_STATUS_T XllpGpioGetDirection (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_GPIO_DIRECTION_T * pDirection);

XLLP_STATUS_T XllpGpioSetDirection (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_GPIO_DIRECTION_T direction);

XLLP_STATUS_T XllpGpioGetRisingEdgeDetectEnable (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_CONTROL_T* pEnabled);

XLLP_STATUS_T XllpGpioSetRisingEdgeDetectEnable  (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_CONTROL_T enable);

XLLP_STATUS_T XllpGpioGetFallingEdgeDetectEnable (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_CONTROL_T* pEnabled);

XLLP_STATUS_T XllpGpioSetFallingEdgeDetectEnable (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_CONTROL_T enable);

XLLP_STATUS_T XllpGpioGetEdgeDetectStatus (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId,
                                XLLP_UINT32_T* pDetectStatus);

XLLP_STATUS_T XllpGpioClearEdgeDetectStatus (
                                P_XLLP_GPIO_T pGPIO, 
                                XLLP_UINT32_T gpioId);

XLLP_STATUS_T XllpGpioSave (
                            P_XLLP_GPIO_T pGPIO, 
                            P_XLLP_GPIO_T pSaveContext);

XLLP_STATUS_T XllpGpioRestore(
                            P_XLLP_GPIO_T pGPIO, 
                            P_XLLP_GPIO_T pSaveContext);
#ifdef __cplusplus
}
#endif



// Begin of Platform GPIO symbolic IDs for each supported ID 

// Any unassigned GPIO IDs are not attached to any pin as an
//  alternate function on this platform.

#if defined(CONFIG_CPU_MONAHANS_P)
#define XLLP_GPIO_MMC_CD_0           1 
#define XLLP_GPIO_DEBUG_ETH_CS_N     3 
#define XLLP_GPIO_MMC_CD_1           4 
#define XLLP_GPIO_MMC_WP_0_N         5 
#define XLLP_GPIO_MMC_WP_1_N         6 
#define XLLP_GPIO_PHONE_CLOSED       7 
#define XLLP_GPIO_PHONE_FLIPPED      8 
#define XLLP_GPIO_DEBUG_ETH_INT      9 
#define XLLP_GPIO_AC97_INT_N        15
#define XLLP_GPIO_CAMERA_STROBE_EN  16
#define XLLP_GPIO_CAMERA_LIGHT_EN   17
#define XLLP_GPIO_MMC_CMD_0			23
#define XLLP_GPIO_MMC_CMD_1			31
#define XLLP_GPIO_MMC2_CMD			29
#define XLLP_GPIO_IR_SHDN_N         97
#define XLLP_GPIO_CFCD 				30
#define XLLP_GPIO_NIRQ 				98
#define XLLP_GPIO_CAMERA_HI_PWDN    102
#define XLLP_GPIO_CAMERA_LO_PWDN    103
#define XLLP_GPIO_CIR_OUT			13
#else

#if defined(CONFIG_CPU_MONAHANS_PL)
#define XLLP_GPIO_DEBUG_ETH_CS_N     3 
#define XLLP_GPIO_DEBUG_ETH_INT      97 
#define XLLP_GPIO_AC97_INT_N        36
#define XLLP_GPIO_CAMERA_STROBE_EN  16
#define XLLP_GPIO_MMC_CMD_0			23
#define XLLP_GPIO_MMC2_CMD			29
#define XLLP_GPIO_MMC_CMD_1			31
#define XLLP_GPIO_CIR_OUT			15
#define XLLP_GPIO_EXP_0_N			12
#define XLLP_GPIO_EXP_1_N			13
#else // L and LV
#define XLLP_GPIO_DEBUG_ETH_CS_N    1
#define XLLP_GPIO_DEBUG_ETH_INT     99 
#define XLLP_GPIO_AC97_INT_N        26
#define XLLP_GPIO_CAMERA_STROBE_EN 	126
#define XLLP_GPIO_MMC_CMD_0			8
#define XLLP_GPIO_MMC2_CMD			14
#define XLLP_GPIO_MMC_CMD_1			15
#define XLLP_GPIO_CIR_OUT			16
#define XLLP_GPIO_EXP_0_N			18
#define XLLP_GPIO_EXP_1_N			19
#endif // #ifdef CONFIG_CPU_MONAHANS_PL


/* kv - For ULPI Reset and Platform Detection for Picoton */

#define	XLLP_GPIO_ULPI_RESET		29
#define	XLLP_GPIO_PLATFORM_DETECT_0_N	0
#define	XLLP_GPIO_PLATFORM_DETECT_1_N	1
#define	XLLP_GPIO_PLATFORM_DETECT_2_N	2
#define	XLLP_GPIO_PLATFORM_DETECT_3_N	3
#define	XLLP_GPIO_PLATFORM_DETECT_4_N	4
#define	XLLP_GPIO_PLATFORM_DETECT_5_N	5
#define	XLLP_GPIO_PLATFORM_DETECT_6_N	6


#define XLLP_GPIO_MMC_CD_0          128
#define XLLP_GPIO_MMC_CD_1          129 
#define XLLP_GPIO_MMC_WP_0_N        130
#define XLLP_GPIO_MMC_WP_1_N        131
#define XLLP_GPIO_PHONE_FLIPPED     132
#define XLLP_GPIO_PHONE_CLOSED      133
#define XLLP_GPIO_USB2_DETECT		134
#define XLLP_GPIO_CFCD				135

#define XLLP_GPIO_CAMERA_LIGHT_EN	136
#define XLLP_GPIO_IR_SHDN_N			137
#define XLLP_GPIO_CAMERA_HI_PWDN	138
#define XLLP_GPIO_CAMERA_LO_PWDN	139
#define XLLP_GPIO_UTMI_TEST_EN		140
#define XLLP_GPIO_UTMI_SWITCH		141
#define	XLLP_GPIO_USB_OTG_EN	    142
#define	XLLP_GPIO_USB_OTG_SR	    143

#define	XLLP_GPIO_GPIO_A			144
#define	XLLP_GPIO_GPIO_B			145
#define	XLLP_GPIO_GPIO_C			146
#define	XLLP_GPIO_GPIO_D			147
#define	XLLP_GPIO_GPIO_E			148
#define	XLLP_GPIO_GPIO_F			149
#define	XLLP_GPIO_GPIO_G			150
#define	XLLP_GPIO_GPIO_H			151

#define	XLLP_GPIO_GPIO_I			152
#define	XLLP_GPIO_MB_SWITCH_A		153
#define	XLLP_GPIO_MB_SWITCH_B		154

#define	XLLP_GPIO_DMARQ				156
#define	XLLP_GPIO_NIRQ				157
#define	XLLP_GPIO_RESERVED1			158
#define	XLLP_GPIO_RESERVED2			159



//#define XLLP_GPIO_CFCD			XLLP_GPIO_CF_CD_N
//#define XLLP_GPIO_NIRQ 			98

#endif // #ifdef CONFIG_CPU_MONAHANS_P

#if defined (CONFIG_CPU_MONAHANS_P) || defined (CONFIG_CPU_MONAHANS_PL)

// usb 2.0 detection
#define XLLP_GPIO_USB_VBUS			46

// for LCD panel id detection
#define XLLP_GPIO_L_VSYNC	74
#define XLLP_GPIO_L_CS		73
#define XLLP_GPIO_L_FCLK	14
#define XLLP_GPIO_L_LCLK	15
#define XLLP_GPIO_L_BIAS	17
#define XLLP_GPIO_L_DD_16	71
#define XLLP_GPIO_L_DD_17	72

// use PWM pin as gpio
#define XLLP_GPIO_BACKLIGHT	14

#else

#define XLLP_GPIO_USB_VBUS			35

#define XLLP_GPIO_L_VSYNC	76
#define XLLP_GPIO_L_CS		127
#define XLLP_GPIO_L_FCLK	72
#define XLLP_GPIO_L_LCLK	73
#define XLLP_GPIO_L_BIAS	75
#define XLLP_GPIO_L_DD_16	70
#define XLLP_GPIO_L_DD_17	71
#define XLLP_GPIO_BACKLIGHT	20

#endif

// End of platform GPIO symbolic IDs

#endif // __XLLP_GPIO_PROC_H__


